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Transactions on High-Performance Embedded Architectures and Compilers II
Per Stenström; David Whalley
Springer-Verlag Berlin and Heidelberg GmbH & Co. KG (2009)
Pehmeäkantinen kirja
49,60
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High Performance Embedded Architectures and Compilers - Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28
Koen De Bosschere; David Kaeli; Per Stenström; David Whalley; Theo Ungerer
Springer-Verlag Berlin and Heidelberg GmbH & Co. KG (2007)
Pehmeäkantinen kirja
49,60
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ostoskoriin kpl
Siirry koriin
Transactions on High-Performance Embedded Architectures and Compilers II
49,60 €
Springer-Verlag Berlin and Heidelberg GmbH & Co. KG
Sivumäärä: 327 sivua
Asu: Pehmeäkantinen kirja
Painos: 2009
Julkaisuvuosi: 2009, 22.04.2009 (lisätietoa)
Kieli: Englanti
Tuotesarja: Transactions on High-Performance Embedded Architectures and Compilers
1 2 Per Stenstro ..m and David Whalley 1 Chalmers University of Technology, Sweden 2 Florida State University, U.S.A. In January2007,the secondedition in the series of International Conferenceson High-Performance Embedded Architectures andCompilers (HiPEAC'2007)was held in Ghent,Belgium.We were fortunate to attract around70 submissions of whichonly19wereselected forpresentation.Amongthese,weaskedtheauthors ofthe?vemost highly rated contributionsto make extended versions ofthem. They all accepted to do that andtheirarticles appear in this section ofthe second volume. The?rstarticlebyKeramidas,Xekalakis,andKaxirasfocusesontheincreased power consumption in set-associativecaches.They presenta novel approach to reduce dynamicpower that leverages on the previously proposed cache decay approach that has been shown to reduce static (or leakage) power. In the secondarticlebyMagarajan,Gupta,andKrishnaswamythe focus ison techniques to encrypt data in memory to preservedata integrity. The problem with previous techniques is that the decryption latency ends up on the critical memory access path. Especially in embedded processors,caches are small and it isdi?cultto hide the decryption latency.
The authors propose a compiler-based strategy that manages to reduce the impact of the decryption time signi?cantly. The thirdarticlebyKluyskensandEeckhoutfocusesondetailedarchitectural simulation techniques.It is well-known that they are ine?cientandaremedy to the problem isto use sampling.When usingsampling,onehastowarm up memory structures such as caches andbranch predictors.Thispaper introduces a noveltechnique calledBranchHistoryMatchingfore?cient warmupofbranch predictors. The fourth articlebyBhadauria,McKee,Singh, and Tyson focuses on static power consumptioninlarge caches.Theyintroduce a reuse-distance drowsy cache mechanism that issimpleas well as e?ective in reducingthestaticpower in caches.

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Helsinki
Tapiola
Turku
Tampere
Transactions on High-Performance Embedded Architectures and Compilers IIzoom
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ISBN:
9783642009037
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