As the supply voltage of circuits decreases to reduce power consumption, analog designs require more physical, accurate, and continuous compact MOS (metal-oxide semiconductor) models. The analog design cycle involves architecture and circuit topology development, current and width/length sizing selection for each MOS transistor, and extensive verification to ensure a high-performance, robust, and high-yielding design for volume production.

Optimizing Analog CMOS Design presents a unique methodology for optimizing analog design, especially at low supply voltages.