In highly mobile, frequently wireless applications like cell phones, personal digital assistants, palmtops and multimedia players the trend is towards smaller and lighter weight packaging yet with increasing functionality and lower price. The demand from end users for increased battery service life is considerable. Reducing on-chip power consumption has become a critical challenge for System-on-Chip (SOC) designers in the nanotechnology era. A new way of thinking about Low power will be necessary to succeed in the consumer electronics arena going forward. Low power design techniques will be used from the earliest phase of the design cycle to have the maximum impact on power convergence and optimization.

As Lead Engineers for Intel and Marvell, respectively, Subhomoy Chattopadhyay and Rakesh Patel work daily at the leading edge of R&D on low power design. This book contains an industry perspective on low power design not currently available, with its focus on the deep sub-micron designs currently needed to achieve the functionality/low-power needs described above. Readers will gain insight into the importance of low power VLSI design microprocessor/SOC and ASIC design from the system, applications point of view. Balancing today's conflicting goals of performance vs low power, this book's realistic, industry-focused coverage demonstrates the importance of low power design from the wireless and handheld communications space to the high end server/workstation space.


* First book to cover in detail low power design for deep-submicron technolgoy nodes (i.e. 65nm, 45nm, and 32nm);
* First book to cover platform power estimation and optimization (ESL);
* Early power estimation and optimization techniques;
* Importance of manufacturing process decisions in power optimization;
* Architectural tradeoffs for low power design;
* State of the art EDA tools used for low power estimation and optimization.