Technical leaders from around the world gather here to discuss developments in the areas of interconnect performance, advanced metallization, low-dielectric constant materials, barrier metallization, atomic layer deposition, advanced packaging and vertical integration. Both current state-of-the-art and ongoing challenges associated with multilevel interconnect are addressed. Included are papers on the latest developments in the integration of low-dielectric constant materials with copper-based metallization, and advances in the understanding of means by which process- or stress-induced damage can be mitigated and reliability of the interconnect system improved. Additional contributions discuss the design, development and modeling of advanced on-chip and multichip interconnect architectures and real-world implementation of optimized designs, materials and processes for production of leading-edge microelectronic devices.