Lalit Garg; Dilip Singh Sisodia; Nishtha Kesswani; Joseph G. Vella; Imene Brigui; Sanjay Misra; Deepak Singh Springer International Publishing AG (2023) Saatavuus: Tilaustuote Pehmeäkantinen kirja
Lalit Garg; Dilip Singh Sisodia; Nishtha Kesswani; Joseph G Vella; Imene Brigui; Peter Xuereb; Sanjay Misra; Deepa Singh Springer International Publishing AG (2022) Saatavuus: Tilaustuote Pehmeäkantinen kirja
Springer Sivumäärä: 182 sivua Asu: Kovakantinen kirja Painos: 2011 Julkaisuvuosi: 2011, 12.05.2011 (lisätietoa) Kieli: Englanti
Since register transfer level (RTL) design is less about being a bright engineer, and more about knowing the downstream implications of your work, this book explains the impact of design decisions taken that may give rise later in the product lifecycle to issues related to testability, data synchronization across clock domains, synthesizability, power consumption, routability, etc., all which are a function of the way the RTL was originally written. Readers will benefit from a highly practical approach to the fundamentals of these topics, and will be given clear guidance regarding necessary safeguards to observe during RTL design.